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双核皓龙2000 曙光A620r-F服务器

  附录A:AMD 1000/2000/8000系列处理器规格表

系列名称 1000 Series 2000 Series 8000 Series
用途 1-way Up to 2-way Up to 8-way
接口 Socket AM2 Socket F (1207) Socket F (1207)
标准功率型  
最大CPU功率 103W 95W 95W
主频 Model Numbers
Next-Generation 1.8GHz Model 1210 Model 2210 -
Next-Generation 2.0GHz Model 1212 Model 2212 Model 8212
Next-Generation 2.2GHz Model 1214 Model 2214 Model 8214
Next-Generation 2.4 GHz Model 1216 Model 2216 Model 8216
Next-Generation 2.6GHz Model 1218 Model 2218 Model 8218
低功率型 HE  
最大CPU功率 - 68W 68W
主频 Model Numbers
Next-Generation 2.0GHz - Model 2212 HE Model 8212 HE
Next-Generation 2.2GHz - Model 2214 HE Model 8214 HE
Next-Generation 2.4 GHz - Model 2216 HE Model 8216 HE
性能优化型 SE  
最大CPU功率 125W 120W 120W
主频 Model Numbers
Next-Generation 2.8 GHz Model 1220 SE Model 2220 SE Model 8220 SE
AMD Virtualization (AMD-V) Yes Yes Yes
Tagged TLB support Yes Yes Yes
Virtualization-aware memory controller Yes Yes Yes
AMD PowerNow!™ technology with OPM Yes Yes Yes
Supported power states Up to 5 Up to 5 Up to 5
Direct Connect Architecture Yes Yes Yes
Integrated DDR2 memory controller Yes Yes Yes
DDR2 Memory type supported Unbuffered Registered Registered
DDR2 Memory controller width 128-bit 128-bit 128-bit
DDR2 Memory Max Frequency DDR2-800 DDR2-667 DDR2-667
DDR2 Memory Max DIMM support/CPU 4 @ DDR2-667 8 @ DDR2-533 8 @ DDR2-533
On-Line spare RAS support Yes Yes Yes
ECC DRAM protection Yes Yes Yes
HyperTransport™ 技术 Yes Yes Yes
HyperTransport technology links (total/coherent) 1/0 3/1 3/3
HyperTransport technology link width 16 bits x
16 bits
16 bits x
16 bits
16 bits x
16 bits
HyperTransport bus frequency 1GHz 1GHz 1GHz
AMD64 Yes Yes Yes
Simultaneous 32 & 64-bit computing Yes Yes Yes
L1 Cache Size (data/instruction) 64KB/64KB 64KB/64KB 64KB/64KB
L2 Cache Size 1MB 1MB 1MB
Pipeline stages (integer/floating point) 12/17 12/17 12/17
L1/L2 data cache protection ECC ECC ECC
L1/L2 instruction cache protection Parity Parity Parity
Global History Counter Entries 16K 16K 16K
L1 TLB entries (data/instruction) 40/40 40/40 40/40
L1 TLB associativity (data/instruction) Full/Full Full/Full Full/Full
L2 TLB entries (data/instruction) 512/512 512/512 512/512
L2 associativity (data/instruction) 4-way/4-way 4-way/4-way 4-way/4-way
SIMD指令支持 SSE, SSE2, SSE3 SSE, SSE2, SSE3 SSE, SSE2, SSE3
生产工艺 90 nanometer SOI 90 nanometer SOI 90 nanometer SOI
产地 Fab 30, Dresden,
Germany
Fab 30, Dresden,
Germany
Fab 30, Dresden,
Germany
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