为核而来 宝德PR1510D四核服务器
缓存内存性能测试
|
ScienceMark Membench | |||
| Xeon5320 x 1 | Xeon5120 x 2 | Xeon5120 x 1 | |
| L1带宽 | 52221.47 | 52358.39 | 52355.24 |
| L2带宽 | 15632.97 | 15683.28 | 15459.64 |
|
内存带宽(MB/s) |
2997.12 | 2918.25 | 2951.25 |
|
L1 Cache Latency (ns) | |||
|
32 Bytes Stride |
1.60 | 1.61 | 1.61 |
|
L2 Cache Latency(ns) | |||
|
4 Bytes Stride |
1.60 | 1.61 | 1.61 |
|
16 Bytes Stride |
2.15 | 2.14 | 2.14 |
|
64 Bytes Stride |
6.44 | 5.89 | 5.89 |
|
256 Bytes Stride |
5.91 | 6.43 | 6.43 |
|
512 Bytes Stride |
6.44 | 6.43 | 6.43 |
|
Memory Latency(ns) | |||
|
4 Bytes Stride |
1.61 | 1.61 | 1.61 |
|
16 Bytes Stride |
2.15 | 2.14 | 2.14 |
|
64 Bytes Stride |
6.44 | 6.96 | 6.43 |
|
256 Bytes Stride |
6.98 | 7.50 | 7.50 |
|
512 Bytes Stride |
7.52 | 8.04 | 8.04 |
|
Algorithm Bandwidth(MB/s) | |||
|
Compiler |
2171.46 | 2068.71 | 2040.59 |
|
REP MOVSD |
2161.72 | 2086.70 | 2075.62 |
|
ALU Reg Copy |
2007.25 | 2019.78 | 1997.65 |
|
MMX Reg Copy |
2055.8 | 2046.38 | 2019.38 |
|
MMX Reg 3dNow |
- | - | - |
|
MMX Reg SSE |
2926.54 | 2906.74 | 2916.17 |
|
SSE PAlign |
2910.06 | 2897.37 | 2932.08 |
|
SSE PAlign SSE |
2997.12 | 2918.25 | 2944.82 |
|
SSE2 PAlign |
2964.91 | 2888.73 | 2919.79 |
|
SSE2 PAlign SSE |
2989.18 | 2917.67 | 2951.25 |
|
MMX Block 4kb |
2410.77 | 2460.69 | 2512.00 |
|
MMX Block 16kb |
2610.58 | 2663.69 | 2708.04 |
|
SSE Block 4kb |
2297.21 | 2452.03 | 2486.21 |
|
SSE Block 16kb |
2631.15 | 2668.89 | 2721.50 |
ScienceMark v2.0 Membench测试仅局限于单个处理器(但是ScienceMark v2.0是可识别并且支持多个处理器的),多个处理器、前端总线结构对于测试结果影响都不大。
|
SiSoftware.Sandra.Enterprise.SP1 v2007 | |||
| Xeon5320 x 1 | Xeon5120 x 2 | Xeon5120 x 1 | |
| Memory Bandwidth | |||
| RAM IntBuff iSSE2(MB/s) | 2773 | 4259 | 2830 |
| Assignment | 2696 | 4265 | 2780 |
| Scaling | 2694 | 4262 | 2778 |
| Addition | 2866 | 4256 | 2893 |
| Triad | 2838 | 4253 | 2869 |
| RAM FloatBuff iSSE2(MB/s) | 2774 | 4257 | 2829 |
| Assignment | 2710 | 4265 | 2784 |
| Scaling | 2698 | 4265 | 2782 |
| Addition | 2854 | 4250 | 2881 |
| Triad | 2835 | 4251 | 2869 |
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SiSoftware Sandra Memory Bandwidth测试会受到前端总线结构的影响,如上表格所示单路四核系统和单路双核系统的内存带宽相似,几乎都是双路双核平台的一半。
Cache and Memory测试结果显示,当测试数据块小于4MB时,单路四核系统和双路双核系统的测试曲线完美的重合在一起,并且它们的带宽基本上是单路双核系统的2倍。
